Many communications and processing devices include circuitry that operates according to clock input signals. Typically, a high frequency master clock signal (CML or CMOS type) is provided by a voltage-controlled oscillator (VCO) or other clock source, and one or more frequency dividers are used to divide the VCO output signal to generate lower frequency clock signals for use by the individual circuits. New applications in the wired and wireless communication space demand higher clock speeds and duty cycle reconfigurability. In addition, many applications require low power clock circuits that can provide a wide variety of overlapping and non-overlapping clock signals, and which are scalable with respect to duty cycle.